1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method and system for polishing a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Frequently, upper surfaces of a semiconductor topography are polished during the fabrication of a device to fabricate layers and structures with planar surfaces. For example, elevational disparities of a dielectric layer used to form an interlevel dielectric layer or shallow isolation trench regions may be reduced by polishing the dielectric layer. In some cases, additional layers and structures such as, contact structures, additional dielectric layers, and/or metallization layers may be formed above such a polished layer or structure. For instance, in an embodiment in which the polished dielectric layer is an interlevel dielectric, a contact opening may be formed within the dielectric layer and subsequently filled with a layer of conductive material. Moreover, the layer of conductive material may be formed within the contact opening and on an upper surface of the polished dielectric layer. Consequently, the layer of conductive material may be polished such that an upper surface of the contact structure may be relatively level with an upper surface of the dielectric layer. In addition, since the polished upper surface of the dielectric layer is planar, the contact structure may have uniform vertical and lateral dimensions. Consequently, the polished upper surface of lower layers and/or structures may facilitate the formation of upper layers and structures having dimensions, which are approximately equal to the design specifications of the semiconductor device.
Forming a substantially planar upper surface of layers and structures may play an important role in the functionality of a semiconductor device. For example, problems with step coverage may arise when a material is deposited over a topological surface having elevationally raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a semiconductor topography may increase with reductions in feature size. In addition, if a topography is non-planar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device. In particular, correctly patterning layers upon a topological surface containing “hill” or “valley” areas may be difficult using optical lithography since all parts of the topography must be within the depth of focus of the lithography system.
As mentioned above, elevational fluctuations in the surface of a semiconductor topography may be removed by polishing the topography. A conventional polishing process may involve placing a semiconductor wafer against a carrier plate, which is surrounded by a carrier ring adapted to prevent movement of the wafer during polishing. The wafer may be pressed face-down toward an underlying polishing pad. During the polishing process, the polishing pad and/or the wafer carrier may be set in motion as the wafer is forced against the pad. In some embodiments, an abrasive, fluid-based chemical suspension, often referred to as a “slurry,” may be deposited onto the surface of the polishing pad. The slurry may fill the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. In addition, the movement of the polishing pad and/or wafer relative to each other may cause abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. Alternatively, the slurry may be substantially absent of particulate matter and/or chemicals. In either embodiment, the pad itself may physically remove some material from the surface of the semiconductor topography.
Unfortunately, conventional polishing processes may not form a substantially planar surface across an entire semiconductor topography. In particular, a semiconductor topography polished by a conventional process may still have substantial elevational disparities, particularly at an edge of the topography. For instance, the thickness variation of a structure at the edge of a polished semiconductor topography may be greater than the thickness variation of a similar structure residing within an inner portion of the topography. Furthermore, the average thickness of the structure at the edge of a polished semiconductor topography may be greater than the average thickness of the similar structure residing within the inner portion of the topography. In either embodiment, such elevational disparities may inhibit the formation of functional semiconductor devices on a portion of the semiconductor topography. For example, a thick region at the outer edge of the semiconductor topography may form semiconductor devices with dimensions, which deviate significantly from design specifications. In this manner, acceptable devices may not be formed within an area of the semiconductor topography having such elevational disparities, thereby reducing the number of devices which may be formed on the semiconductor topography. As such, the presence of such elevational disparities on a semiconductor topography may reduce manufacturing yield and may increase production costs per semiconductor device.
In some embodiments, the assembly of the wafer carrier of the polishing system may contribute to the formation of elevational disparities across the semiconductor topography. In particular, the manner in which the carrier ring is coupled to the carrier plate may contribute to the formation of elevational disparities across the semiconductor topography. In conventional polishing processes, bolts may be used to couple the carrier ring to the carrier plate. In particular, bolts may be screwed into aligned openings of the carrier plate and carrier ring. Frequently, however, the bolts may be over-torqued, warping the carrier ring and/or carrier plate and resulting in a poor attachment of the two components. Such a poor attachment may allow regions of the wafer to be brought closer or farther away from the polishing pad. Such a “toggling” of the wafer may cause a variation of the polishing process, resulting in elevational disparities across the wafer.
Another problem associated with the warping of the carrier ring and/or carrier plate is that the protrusion of the wafer extending from the carrier ring toward the polishing pad may undesirably deviate from its specified dimension. Typically, it is beneficial for the wafer to extend from the carrier ring by a certain amount such that the carrier ring does not interfere with the polishing process (i.e., such that the carrier ring does not come into contact with the polishing pad during the polishing process). However, warping of the carrier ring and/or carrier plate may cause the protrusion of the wafer to change, compromising the functionality of the polishing system. Consequently, shims are sometimes placed between the carrier ring and carrier plate to compensate for such a change in the carrier ring thickness. Unfortunately, the assembly and reassembly of a wafer carrier with shims may be time consuming and therefore, costly. In particular, the protrusion of a wafer extending from the carrier ring may have to be measured after each wafer carrier assembly to insure that the shims position the wafer within the process specifications of the polishing system. In addition, such a protrusion measurement is typically measured manually and therefore, may introduce an increase in process variation due to human-error occurrences.
Accordingly, it would be advantageous to develop a polishing system, which does not require the use of shims to insure a protrusion of a wafer extending from a carrier ring is within the process specifications of a polishing process. In particular, it would be beneficial to develop a polishing system, which yields a protrusion within process specifications upon coupling a carrier ring to a carrier plate. In addition, it would be advantageous to develop an improved method for coupling a carrier ring to a carrier plate. In particular, it would be beneficial to develop a polishing system, which does not cause the carrier ring and/or carrier plate to be warped.